The present invention relates to a MOSFET (metal oxide semiconductor field effect transistor) device; and, more particularly, to an ultra small size vertical MOSFET device having a vertical channel and a source/drain structure and a method for the manufacture thereof by using a silicon on insulator (SOI) substrate.
In a silicon device technology, it is necessary to reduce a length of a channel, a depth of metallurgical junction at source and drain contact and a thickness of an effective gate insulating layer for achieving the silicon device with a low voltage, a high integration and a high speed drivability. Additionally, it is required the device with a high performance characteristic by an increase of a driving current and a decrease of a leakage current among the same size of the devices.
However, it has lot of obstacles to manufacture a nano-scale silicon device with a high performance by using a conventional manufacturing method. That is, in case of manufacturing a planar channel of a nano-scale by the conventional method, a special patterning method such as an e-beam direct writing method or x-ray lithography method should be used. But it is impossible to manufacture the nano-scale silicon device in large quantities because the e-beam direct writing method and x-ray lithography method are not definite techniques up to now. Furthermore, since it is not only difficult to fabricate the nano-scale device with shallow source/drain junction depth using a single crystal silicon material but an electrical isolation property may also be deteriorated, there are difficulties in fabricating the device with the low voltage drivability. Thus, in order to overcome the above problems, very complicated manufacturing processes are required.
One conventional method for manufacturing a vertical MOS transistor is disclosed by Mitsui in U.S. Pat. No. 5,382,816, xe2x80x9cSemiconductor Device Having Vertical Transistor with Tubular Double Gatexe2x80x9d. In accordance with this method, a first gate and a second gate are formed the interior and the exterior of the vertical channel. Thus, a threshold voltage may be controlled by applying voltage to each gate. However, this method has drawbacks that a structure of the MOS transistor is too complicated and further, a plurality of lithography, deposition and etch processes are required. Additionally, it is hard to downsize the device because it is difficult to secure a process margin.
Another conventional method for manufacturing a vertical MOS transistor is disclosed by Kenney in U.S. Pat. No. 5,365,097, xe2x80x9cVertical Epitaxial SOT transistor, Memory Cell and Fabrication Methodsxe2x80x9d. In a disclosure, a trench is formed on an SOI substrate and a silicon epi layer is deposited in the trench. Therefore, a memory cell and the MOS transistor fabricated integrally. However, the MOS transistor having the vertical silicon channel in accordance with this conventional method has disadvantages as follows: first, it is difficult to secure a process margin owing to a complicated structure of the device; second, it is hard to fabricate the device in the trench of a micro size; third, it is difficult to grow up a single crystal silicon epi layer on a poly-crystal silicon; fourth, it is difficult to form a p-n junction on the channel of the single crystal and a diffusion layer of the poly-crystal; fifth, since source/drain regions are formed on the channel of the single crystal and a diffusion layer of the poly-crystal, the junction leakage of source/drain regions increases, besides a reliability and an insulating property of a gate insulating layer may be deteriorated.
The other conventional method for manufacturing a vertical MOS transistor is disclosed by J. M. Hergenrother in an article, xe2x80x9cThe Vertical Replacement-Gate MOSFET, IEDM 99, pp. 75-78, Dec. 1, 1999xe2x80x9d. In the article, the method comprises the steps of forming a trench using a single crystal silicon substrate, forming a vertical channel by growing up the single crystal silicon epitaxially, forming a gate enclosing the channel, and forming a source/drain over and below the gate. According to this method, in order to fabricate the MOS transistor having the vertical silicon channel, complicated manufacturing steps should be carried out. Namely, a trench is formed interior of an insulating layer, first of all. Thereafter, the single crystal silicon epi layer is formed in the trench. Finally, the source/drain is formed. Therefore, it has problems that the manufacturing processes are too complicated and further, it is difficult to interconnect among the unit devices.
As described above, in accordance with the conventional methods, an isolation step is required due to a use of the bulk silicon. Moreover, stringent manufacturing conditions are needed in order to reduce the length of the channel. That is, because it is impossible to form the channel of the nanometer size horizontally by using a conventional photolithography, the e-beam direct writing method or x-ray lithography method should be employed. Although the e-beam direct writing method or x-ray lithography method is used, it is difficult to manufacture the device of nano-meter size in large quantities. The lithography technique is not established in order to manufacture the device of the nanometer size still now. In addition, the conventional method using the silicon single crystal has large problems for forming shallow source/drain junction, ensuring a reliability of the nanometer scale device and isolation of each device electrically.
It is, therefore, an object of the present invention to provide an ultra small size vertical MOSFET (metal oxide semiconductor field effect transistor) device having a vertical channel and a source/drain structure by applying a diffusion process without additional lithography steps.
It is another object of the present invention to provide a method for manufacturing an ultra small size vertical MOSFET device having high drive current by increasing the channel width in the same chip area.
In accordance with one aspect of the present invention, there is provided the ultra small size vertical MOSFET device, comprising: a silicon on insulator (SOI) substrate including a single crystal substrate, an oxide layer formed upon the single crystal substrate and a first single crystal silicon layer formed upon the oxide layer; a first silicon conductive layer formed by doping an impurity of a high concentration into the first single crystal silicon layer; a source region, a channel and a drain region formed on the first silicon conductive layer; a gate insulating layer formed on the first silicon conductive layer, the source/drain regions and the channel; a second silicon conductive layer formed on the drain contact; and a gate electrode formed on side walls of the channel.
In accordance with another aspect of the present invention, there is provided a method for manufacturing an ultra small size vertical MOSFET device, the method comprising the steps of: a) preparing an SOT substrate including a single crystal substrate, an oxide layer formed upon the single crystal substrate and a first single crystal silicon layer formed upon the oxide layer; b) forming a first silicon conductive layer by doping an impurity of a high concentration into the first single crystal silicon layer; c) forming a second single crystal silicon layer and a second silicon conductive layer on the first silicon conductive layer, wherein the second single crystal silicon layer has the impurity of a low concentration and the second silicon conductive layer has the impurity of a high concentration; d) patterning the second silicon conductive layer and the second single crystal silicon layer vertically into a first predetermined configuration; e) forming a gate insulating layer on the first silicon conductive layer, the second single crystal silicon layer and the second silicon conductive layer; f) carrying out an annealing process to diffuse the impurities in the first silicon conductive layer and the second silicon conductive layer into the second single crystal layer, thereby forming a source region, a drain region and a vertical channel; and g) forming a gate electrode on side walls of the vertical channel, wherein the gate electrode encompasses the channel.